Today more than ever, we need high-speed circuits with low occupancy and low power as an alternative to CMOS circuits. Therefore, we proposed a new path to build nanoscale circuits such as Quantum-dot Cellular Automata (QCA). This technology is always prone to failure due to its very small size. Therefore, designers always try to design fault-tolerant gates and provide methods to increase the reliability of QCA. By adding redundant cells, the possibility of some defects such as cell omission and cell addition is somewhat reduced. However, in the face of defects such as stuck-at 0/1 faults, Clock fault and bridging fault. We can greatly increase the fault tolerance by appropriate placement and using fault tolerant gates with a suitable structure. In this paper, we design the XOR/XNOR gate with the approach of preventing stuck-at 0/1 fault, clock fault, and bridging fault using the first NNI gate tolerating cell addition fault.

Over the years, the design and implementation of fault-tolerant circuits have been one of the main concerns of the designers of electronic devices. Quantum Dot Cellular Automata (QCA) is a low-power, compact technology that is prone to various defects due to its small size. We can categorize these defects into three main groups: operational defects, manufacturing defects, and clocking defects. Using redundant cells, fault-tolerant gates, or changing the structure of the gates can improve the overall fault-tolerance of the circuit in some cases. However, increasing the fault-tolerance would lead to an increase in the occupied area and the delay of the gates. Therefore, designing a gate based on intercellular interactions with a minimum number of cells and maximum efficiency, which is also fault-tolerant, is a challenging task. In this paper, we present a new tile-shaped design for XOR and XNOR gates that is robust to the Missing cell, Extra cell, and Rotated cell defects by 25%, 55%, and 25%, respectively. That is why we call these gates TFXOR and TFXNOR, respectively.

Quantum Cellular Automata (QCA) is one of the main substitutes for CMOS technology and it is used in implementation of different systems. Manifest features including high speed and low power consumption increase the subject of the QCA in research. However, the extensive possibility of occurrence of defects and appropriate physical implementation in the QCA is one of fundamental challenges in using such technology. In this study, basic details about nanotechnology and related discussions to the fault tolerant in this field are presented. In addition, by investigation on several XOR gates, two novel XOR gates are proposed, these gates were designed by using fault tolerance tile structures. Afterwards, for determining the optimum gate, the tolerance rate of these gates against missing cell defects were investigated. Simulation results showed that proposed gates have more tolerance against missing cell defects.

A novel technique for creating logic gates and digital circuitry at the nanoscale is quantum cellular automata (QCA). The sensitivity of the circuit is enhanced and quantum circuits are more susceptible to unfavorable external conditions when component size are reduced. In this article, we offer a five-input majority gate with fault-tolerant feature in QCA technology, taking into account the significance of constructing circuits that can withstand flaws. We also assess all potential defects in the process of arranging cells in specific locations on the surface. These errors consist of extra cells, rotation, deletion, and displacement. The gate under study is subjected to the aforementioned four failure categories in the first stage. The QCADesigner simulator engine is then used to assess the accuracy of the circuit performance in the second step. 41 quantum cells have been used to make the gate of this five-input majority gate with fault-tolerant feature in QCA technology. Several techniques are explored to discover such a majority gate, such as adding cells (i.e., introducing redundancy into the circuit) and particular cell layout techniques. The goal is to come up with a design that can ideally withstand possible faults with the least amount of overhead on the circuit for fault-tolerant through a certain cell layout. The findings demonstrate the implemented majority gate's notable advantage over comparable scenarios.

Quantum-dot Cellular Automata (QCA) is anemerging technology and one of the suitable alternativesto conventional CMOS technology. Designing efficientbasic logic circuits like decoders is an open research topicin this emerging technology. As reliability is also the mostimportant issue in QCA technology circuit design due toits susceptibility to faults occurring during chemicalfabrication, we design an efficient coplanar robust 2-to-4decoder, employing a novel fault-tolerant three-inputmajority gate. Our proposed majority gate is designedwith 11 simple QCA cells. The area and energyconsumptions of the proposed majority gate is 0.01 μm2and 1.49×2-2 MeV, respectively. The presented majoritygate has also 71% and 100% tolerance against single-cellomission and extra-cell deposition defects, respectively,and it has a proper tolerance against cell displacement andmisalignment defects. The novel robust 2-to-4 decoder isalso designed using the proposed majority gate. Thesimulation results show that the presented decoder is moreefficient in comparison to previous designs.

Quantum dot Cellular Automata (QCA) is one of the important nano-level technologies for implementation of both combinational and sequential systems. QCA have the potential to achieve low power dissipation and operate high speed at THZ frequencies. However large probability of occurrence fabrication defects in QCA, is a fundamental challenge to use this emerging technology. Because of these various defects, it is necessary to obtain exhaustive recognition about these defects. In this paper a complete survey of different QCA faults are presented first. Then some techniques to improve fault tolerance in QCA circuits explained. The effects of missing cell as an important fault on XOR gate that is one of important basic building block in QCA technology is then discussed by exhaustive simulations. Improvement technique is then applied to these XOR structures and then structures are resimulated to measure their fault tolerance improvement due to using these fault tolerance technique. The result show that different QCA XOR gates have different sensitivity against this fault. After using improvement technique, the tolerance of XOR gates have been increased, furthermore in terms of sensitivity against this defect XORs show similar behavior that indicate the effectiveness of improvement have been made.